FIG. 1 is a schematic block diagram indicating the main functional components of a 3GPP wideband code division multiple access (WCDMA) receiver. Reference numeral 2 denotes an antenna which receives a wireless transmission and supplies it in analog form to RF and IF stages 4. A receiver front end 6 includes the functions of analog to digital conversion and supplies digital samples to a signal detection block 8. The signal detection block 8 can be implemented in a number of ways and is responsible for de-scrambling and de-spreading the received coded signal samples. For each transmission time interval (TTI) data is received which comprises a plurality of transport channels (TrCH) multiplexed onto a dedicated physical channel (DPCH in 3GPP WCDMA). The signal to interference plus noise ratio (SIR) of the received signal can be measured from the output of the signal detection block 8, in an SIR estimation block 9. The output of the signal detection block is then fed to a channel decoding block 10. As shown in FIG. 1, after signal detection and channel decoding the decoded data bits are supplied to a Cyclic Redundancy Check (CRC) block 12. The CRC check indicates whether or not the data block has been correctly decoded.
For interference-limited wireless systems, such as those based on CDMA technology, link adaptation is performed by a Transmit Power Control (TPC) mechanism, which ensures that sufficient but not excessive power is transmitted to achieve an adequate received signal quality. In a 3GPP WCDMA system, the power control mechanism comprises two parts: 1) a so-called “outer-loop” algorithm 14 that sets and adjusts a target signal to interference plus noise power ratio (SIR) in order to meet a Block Error Rate (BLER) target set by a network; and 2) a so-called “inner-loop” algorithm 16 that provides fast feedback to the transmitter in order that the transmitter can adjust its transmitted signal power so that the receiver SIR target is met. The inner-loop transmit power control 16 is typically based on the comparison between a target SIR (SIRtarget) and an SIR estimated from the received signal (SIRest). The outer-loop mechanism 14 increases or decreases the SIR target in response to the receipt of block error information, which is typically derived by the pass/fail of the CRC check 12. If a data block is received correctly (CRC pass) then the SIR target is decreased; if a data block is received incorrectly (CRC fail) then the SIR target is increased. In a typical implementation, the amount the SIR target is decreased following a correctly decoded block is equal to some step size (in dB) multiplied by the target block error rate, and the amount the SIR target is increased following an incorrectly decoded block is equal to the step size multiplied by one minus the target block error rate. For example, for a 10% BLER target and a 1 dB step size, the SIR target will be decreased by 1*0.1=0.1 dB following a good block and increased by 1*(1−0.1)=0.9 dB following a bad block. This has the effect that, for typical BLER targets, many more good blocks are required to lower the target than bad blocks to raise it by the same amount. In normal circumstances, the inner-loop power control is able to adjust the transmitted power to meet the new target in a short period (in WCDMA the power can be changed by 1 dB per slot).
In the case where multiple transport channels are multiplexed on a single Dedicated Physical Channel (DPCH) then the DPCH's SIR target is derived from the SIR targets of the individual TrCHs (e.g., by taking the largest SIR target). If one or more of the TrCHs carries bursty traffic, e.g., from a Signaling Radio Bearer (SRB), with large periods of inactivity during which its SIR target is not updated, the DPCH's SIR target may be pinned at an unnecessarily high level and will be unable to respond to either improvements in the radio environment or the looser SIR requirements of the other (active) TrCHs. Such behavior has a negative effect on cell capacity and may lead to the call being dropped by a high layer Radio Resource Management (RRM) algorithm.
It is an aim of the present invention to provide an outer-loop power control mechanism which obviates or at least mitigates the above disadvantages.